Secure high assurance communications, for example, using the HAIPIS Version 3.1 (High Assurance Internet Protocol Encryption Interoperability Specification) developed by the National Security Agency, are becoming more commonplace. Developers are actively pursuing embedments of new, secure high assurance communications with requirements for real time packet analysis that includes statistics gathering and packet control used for covert channel and bypass communications. Depending on the underlying channel capacities or other aspects of individual applications, different levels of performance may be required demanding enhanced packet analysis.
One challenge is to provide a hardware platform that provides the required level of computational support for a packet analyzer, but is optimized with respect to cost, size, weight and similar factors that developers actively pursue and seek. It is often difficult for developers to scale any packet analyzer to a small size with low power applications and a lower throughput and latency without significant architectural changes in the packet analyzers. The cost changes non-linearly with performance requirements such as for non-recurring engineering (NRE) and recurring engineering (RE) requirements.
Many packet analyzers are software intensive. Performance scaling in some of these systems is achieved by varying the processing and memory resources. Although this type of modification has been found acceptable in some packet analysis applications, any achieved performance scaling makes it difficult to obtain high throughput rates and obtain a low latency. It is also difficult to customize for specific customer requirements because of bypass policies and real-time packet analysis issues, including requirements for statistics gathering and packet manipulations.